A variety of multiple bit counter circuits are realized by connecting flip-flop circuits with multi-input Boolean logic circuits. Counter circuits are often characterized by their numerical counting ability, usually expressed as the number of bits. When the number of bits in a counter circuit increases, this drives the requisite number of associated Boolean logic gates to also increase. Typically the number of Boolean logic gates increases exponentially in relation to the number of bits. This requisite increase in Boolean logic gates is usually schematically represented by two interchangeable and equivalent methods. The objective of both methods is the same: to accommodate additional requisite logic variables. Suppose we wish to add two logical input variables C and D to a logical expression A.multidot.B=O. The first method is to implement a Boolean logic gate that has two additional gate inputs to accommodate additional logical variables, for example, a two input AND gate's capacity is increased by implementing it with four inputs, such that A.multidot.B.multidot.C.multidot.D=O. The second method is to implement several Boolean logic gates connected as a group to accommodate additional requisite logical terms. Returning to the AND gate example, it is well understood that a four-input AND gate can be achieved by connecting each output of two-input AND gates into each input of a two-input AND gate. The result is a four-input AND gate constructed from three two-input AND gates. Expressed in Boolean logic notation (A.multidot.B).multidot.(C.multidot.D)=O.
Typically as each additional bit is added to a counter circuit, the requisite additional Boolean logic increases as well. The Boolean logic is connected in distinct successive levels, e.g., one level of Boolean logic for two bits, another level of Boolean logic for four bits. A four bit counter circuit will typically have two or more levels of Boolean logic. The increase in the number of levels of Boolean logic levels necessary to accommodate an increased counter bit length, may not pose problems in theory, but practically it has several undesirable effects. The first undesirable effect is an increase in propagation time that reduces the maximum speed of operation. The second is that the increase in the levels of circuitry results in larger circuit sizes, more complicated interconnections, higher fabrication costs, and higher power consumption. Commercially available binary counters such as the SGS-Thomson family of binary counters 74HC160, 74HC393, 74HC590, 74HC4017, each requires multiple levels of logic to count and reset.
U.S. Pat. No. 5,361,289 issued Nov. 1,1994, to Kawano for "Synchronous Counter Circuit Having a Plurality of Cascade-Connected Counters" discloses a synchronous counter circuit comprising first and second counting circuits and a latch circuit. This counter has "ripple" combinatorial logic terms, which require multiple levels of logic for implementation.
U.S. Pat. No. 5,526,393 issued Jun. 11, 1996 to Knodo et al for "Synchronous Counter" discloses a synchronous counter circuit with a D flip-flop, and a J-K flip-flop, wherein each counter stage is connected by two or more levels of Boolean logic to count and reset.
Thus, a need exists for a high speed synchronous counter circuit realized with a minimum number of levels of Boolean logic.